PLL's in Cyclone V

Hello,

Apologies for the delay. I conducted a lot of trial and error tests. I am not sure if this is the way to go about.

This is the top level code:

module top(

input clk,

input rst,

input driver_clk,

output pll_out,

output locked_port,

output data

);

driver d1(

.clk(driver_clk),

.rst(rst),

.data_out(data)

);

pll pll_inst (

.refclk (clk), // refclk.clk

.rst (rst), // reset.reset

.outclk_0 (pll_out), // outclk0.clk

.locked (locked_port) // locked.export

);

endmodule

I am using PIN_AF14(clk) as the refclk for the PLL, I am assigning the output from the PLL (outclk) to PIN_AH12 and I am using the PIN_AJ12 as the input to the 'driver' module. The scope shows the increase in frequency. But there is lotta noise and jitter in the output signal from the HSMC PIN_B13. I have also made the outclk from the PLL as GCLK.

Is this the right way to go about? Thanks for all your help.