PLL Warnings appearing with Quartus Prime

Hi,

Looks like the cnt_sel[4:0] does not have any drivers. Due to this, the optimization tool has removed away the logic and signals associated with these 5 counter select lines. You should check if these 5 bits are being driven by any logic. If not, then you can ignore the warnings.

Hi,

Thanks for your reply... I already checked the so-called "validity" of these warnings to find out that indeed I can ignore them.

My concern is more about the fact that the same design doesn't generate any warning with Quartus II v15.0.2.

It's always a bit unsettling when the synthesizer informs you that it threw away some part of a design !

To know if necessary PLL functionality has been discarded, you need to know what the designed functionality is. That's not obvious from the quoted warnings.

It can be better seen in the fitter resource utilization report. How is the PLL instantiated? If it's Megawizard generated IP, did you regenrate it with the recent Quartus version?

Hi,

From what I can see in the fitter resource utilization report the three PLLs seem to be implemented correctly. The IPs were re-generated (using Megawizard) when I moved from v15 to Prime v17. The IP components panel says that the IPs are Altera PLL v17.1 and up-to-date.

In my VHDL I copy the component declaration from the .cmp file generated by Megawizard in the declaration section and then I instantiate the component in the behavioral section.

Here again, the design works as expected ! My only concern is about these somehow destabilizing warnings saying that the synthesizer threw away parts of the design !