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RLee42's avatar
RLee42
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

PLL warning about clkin pin location

My project has this warning Warning: PLL "PLL:inst_PLL|altpll:altpll_component|PLL_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance ...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Is the clock pin feeding only the PLL or does it feed any other block in the design apart from the PLL.? sometimes this warning can occur if the input clock feeds another block apart from the PLL inclock.