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number_7's avatar
number_7
Icon for New Contributor rankNew Contributor
2 years ago

PLL placement warning

ATX/PLL is not placed in same bank as reference clock

During fitter phase i am getting this warning message. how to fix this and this will cause any timing issues related to the clocking path from the PLL.

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3 Replies

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    May I know if you can share the screenshot of the full error message of this issue?


    Regards,

    Aqid


  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    As we do not receive any response from you on the previous reply have been provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you by replying to this thread.


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