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New Contributor

2 years ago

PLL placement warning

ATX/PLL is not placed in same bank as reference clock During fitter phase i am getting this warning message. how to fix this and this will cause any timing issues related to the clocking path from ...

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AqidAyman_Altera

Regular Contributor

2 years ago

As we do not receive any response from you on the previous reply have been provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you by replying to this thread.

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PLL placement warning

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