PLL output have the wrong phase

I ran into this problem as well. It happens if you have multiple outputs from the PLL that have a phase relationship to each other. When your PLL loses lock, the PLL loop is basically out of whack while it tries to regain lock. While that is happening, the clocks to the output counters can get out of sync. If that happens and your PLL regains lock, the phase relationship between your outputs could be off.

The best thing to do is to reset the PLL once you lose lock. You can make a simple circuit that looks for lock to go low and then waits a bit of time before asserting areset. Caution: if you simply tie the inverse of "locked" to the areset port of the PLL, your PLL will be in a constant loop of resetting itself. You need a wait timer to make sure this doesn't happen.

Go A's.

-RM