Forum Discussion

fogl's avatar
fogl
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

PLL not fully compensated because it is fed by a non-dedicated input

Hello everybody, I am having problem with error messages about the PLL: Warning (15062): PLL in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because ...
fogl's avatar
fogl
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Let me answer to myself. The problem is that the this device has only one PLL, not two as i assumed from the M10 Overview - Table4. The PLL1 has to be connected to ckj0/clk1 input to be fully compensated, but in my case it is connected to clk3.

Regards