PLL locking and reset generation in Cyclone III

FPGAs are supplied with internal reset that is released after configuration is finished. Designers can apply reset values to their FF or set the global feature "Powerup don't care" to false.

The problem is that, while this in principle works, however any reset release has its own problems unless synchronised to its clk domain.

Thus a safe way is to wait for PLL to lock ..etc applying your own reset then release resets synchronised per clk domain.Your own reset can be external or even internal using some initial logic that is protected from release problems e.g. counter starting at 0 until 3 then stop and release the reset.

I normally apply raw reset to PLLs then synchronise it per clk domain and release it connected to asynchronous ports of FFs.

Additionally, I use internal feddback reset from modules just in case.

Note some people use the so called synchronous reset Vs asynchronous but I am sure synchronous is meaningless unless signal is synchronised at source and then applying it to D or Q of FF makes no difference but to resource usage...