pll_lock does not lock but the pll works

Hello,

If i'm not wrong pll_lock works by positive logic, so i have this problem: My PLL Works but doesn't lock, anyone knows why?

http://i46.tinypic.com/11lshsg.jpg

As you can see CLOCK_25 is undetermined but doesn't matter if i init it as 0 or no init, it remains X. this may be the cause of all, but i continued programming cause the signal seemed to generate ok.(Obviusly i don't understan why there is an X since i don't write there anywhere, except the initialization.)

My pll code is this:

component ===>

BlocPLL: PLL port map (clock_27,clock_25,pll_lock);

ENTITY PLL IS

PORT

(

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

END PLL;

Thanks

PS: The main reason of this post is i've got the PLL_Lock atached to the nReset so i would prefer it to work.