Forum Discussion
Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- As said, the PLL model is simulating some locking delay (in a 10 µs range, if I remember right). --- Quote End --- Ok, sorry, my time period is 40 ns so it should lock in about 300 clocks, my window of 10 clocks is clearly insufficient, that may be a reason. --- Quote Start --- Finally, PLL simulation doesn't work with default ns Modelsim timescale, it has to be changed to ps. --- Quote End --- Why more precision?, Thank you.