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lambert_yu's avatar
lambert_yu
Icon for Contributor rankContributor
1 year ago
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PLL IP simulation under UVM simluation environment

Hi, quartus version : 19.1 IP : IOPLL & FPLL issue : Now, I integrated fpga into asic simulation environment which use uvm, I made sure I have input all fpga libraries and simulation model, and th...
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  • WZ2's avatar
    WZ2
    1 year ago

    Hi Lambert,

    Generally speaking, our IP is not simulated using UVM. If the issue is solely due to the use of UVM, which causes different results, then I suspect that the issue may not be related to UVM’s handling of the reset/input clock, but rather that the library might not fully support UVM.

    Best regards,

    WZ


WZ2's avatar
WZ2
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi Lambert,

Generally speaking, our IP is not simulated using UVM. If the issue is solely due to the use of UVM, which causes different results, then I suspect that the issue may not be related to UVM’s handling of the reset/input clock, but rather that the library might not fully support UVM.

Best regards,

WZ