ContributorPLL IP simulation under UVM simluation environment
Hi,
quartus version : 19.1
IP : IOPLL & FPLL
issue : Now, I integrated fpga into asic simulation environment which use uvm, I made sure I have input all fpga libraries and simulation model, and there's no any warning and error. But when I provided correct reset and refclk to IP. there's no any ouptut (lock is '0', output clock is '1'). But the same design could work without uvm. So if I want to get correct simulation result, which configuration will I need to add or IP model of fpga could not be used under uvm simulation environment? Could someone help to provide some information? Thanks!
Best Regards,
Lambert
Hi Lambert,
Generally speaking, our IP is not simulated using UVM. If the issue is solely due to the use of UVM, which causes different results, then I suspect that the issue may not be related to UVM’s handling of the reset/input clock, but rather that the library might not fully support UVM.
Best regards,
WZ
