http://quartushelp.altera.com/14.0/mergedprojects/msgs/msgs/ecclk_pll_refclk_not_from_dedicated_refclk.htm
As that is a hardware limitation of the routing inside the FPGA, I think you may be limited to two solutions.
Admittedly, I doubt that either solution will make you happy.
1) Re-spin the board
2) Feed in the clock frequency you want instead of using a PLL. This may require a custom crystal oscillator.
One last-ditch option would be to short between any unused clock-input pin and an adjacent unused GPIO pin.
Then you can route your clock though the FPGA's logic fabric as an asynchronous signal, and out of that GPIO pin.
Then your clock signal will go out, and then back in to the chip on a dedicated clock-input pin that can have a PLL associated with it.
Check your schematic, and on Quartus's pin planner to see which pins might be suitable for this work-around.
Good luck.
Honored Contributor
