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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

PLL Implemantation

Hi, During the compilation of a quartus design, the following messages appears: Warning: PLL "pll_name" input clock inclk[0] is not fully compensated and may have reduced jitter performanc...
Moki's avatar
Moki
Icon for New Contributor rankNew Contributor
7 years ago

I had a similar problem, because my input clock was marked as a global clock.

Removing this from my .qsf file solved the issue:

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk