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Altera_Forum
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18 years ago

PLL Implemantation

Hi, During the compilation of a quartus design, the following messages appears: Warning: PLL "pll_name" input clock inclk[0] is not fully compensated and may have reduced jitter performanc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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Ignore the warning.

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What if it's a critical warning? :o

I have this design on Cyclone 3 that has a clock (14MHz) input from a dedicated clock pin, prompted as global clock by the fitter automatically because it is used in many places. Then this clock is used as the input for two plls to generate 3 other clocks (can't be merged into 1 pll). Now the fitter is giving the same warning was discussed in this thread but it's critical. Can it be ignored? What does the compensation do anyway?

I also tried cascade the plls in a way that the clock pin is connected to one of the plls, and that pll generates another 14MHz clock which is used as an input for the second pll and also for being used in the other part of the design. That doesn't seem to work well because it takes much longer to fit and when it does finish fitting I got many timing violations.... Don't know if it's related to the clock tree change. Any thoughts?

Hua