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Altera_Forum
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18 years ago

PLL Implemantation

Hi, During the compilation of a quartus design, the following messages appears: Warning: PLL "pll_name" input clock inclk[0] is not fully compensated and may have reduced jitter performanc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

You can't "dedicate" the input and output pins of a PLL they are hard wired to pins and defined in the pin out files for each FPGA.