PLL generates some unwanted frequency

Hi

I want to interface SDRAM with the Cyclone III FPGA, actually I had successfully interface the SDRAM with Cyclone III FPGA but the problem is when I disable the SDRAM clock (connect the clock pin to the GND) my system noise hugely decrease and then I enable the SDRAM clock (connect to the SDRAM IP core) it generates lot of noise and unwanted frequency (noise increase +20dbm with respect to the other situation)

SDRAM clock frequency is 100MHz with -60deg phase shift but the output on the spectrum analyser shows a lot of unwanted frequency

SDRAM clock is generated using cyclone III PLL

Could anyone please suggest a solution to eliminate the unwanted frequencies?

Best Regards