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Altera_Forum's avatar
Altera_Forum
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12 years ago

PLL generates some unwanted frequency

Hi I want to interface SDRAM with the Cyclone III FPGA, actually I had successfully interface the SDRAM with Cyclone III FPGA but the problem is when I disable the SDRAM clock (connect the cloc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

What is "system noise" for you? Where do you connect a spectrum analyzer? Are you talking about radiated interferences?

Generally speaking, a SDRAM in operation will always generate some noise. It strongly depends on your PCB design if it's kept inside the digital circuit or is spread over the system and radiated.