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Joossss's avatar
Joossss
Icon for New Contributor rankNew Contributor
5 years ago
Solved

PLL frequency doubling but shouldn't

Hey! I'm using a PLL on Cyclone 10 LP to create a clock with the same frequency, but shifting the phase. The PLL works fine in simulation when I create a clock and feed it straight into the PLL. Ho...
  • Ash_R_Intel's avatar
    Ash_R_Intel
    5 years ago

    Hi Joossss,


    Thanks for your code!

    I was able to reproduce the issue that you mentioned.

    In the screen shot that you had shared, the output of the LVDS_CLK_inst (buffer) is not clean. There are some red lines ('X') on the buffer output. Same happened in my code as well (see signal /top_tb/dut/clk_in) . Result was that the PLL output was double the input clock.

    Then in the test bench, instead of using the procedure clk_gen, I drove the differential clock inputs using simple process.

    SIGNAL clk_in_p : STD_LOGIC := '1';

    SIGNAL clk_in_n : STD_LOGIC := '0';


    PROCESS

    BEGIN

    clk_in_p <= not clk_in_p;

    clk_in_n <= not clk_in_n;

    WAIT FOR 6.6666 ns;

    END PROCESS;


    With this the buffer output was clean and the PLL generated the output as expected. See the screen shot.


    May be due to the 'procedure' there is an delta delay added to the input signals and they are not phase aligned to each other, so the buffer output is not clean.

    That impacted the PLL output as well.


    Regards.


Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Joossss,


Thanks for your code!

I was able to reproduce the issue that you mentioned.

In the screen shot that you had shared, the output of the LVDS_CLK_inst (buffer) is not clean. There are some red lines ('X') on the buffer output. Same happened in my code as well (see signal /top_tb/dut/clk_in) . Result was that the PLL output was double the input clock.

Then in the test bench, instead of using the procedure clk_gen, I drove the differential clock inputs using simple process.

SIGNAL clk_in_p : STD_LOGIC := '1';

SIGNAL clk_in_n : STD_LOGIC := '0';


PROCESS

BEGIN

clk_in_p <= not clk_in_p;

clk_in_n <= not clk_in_n;

WAIT FOR 6.6666 ns;

END PROCESS;


With this the buffer output was clean and the PLL generated the output as expected. See the screen shot.


May be due to the 'procedure' there is an delta delay added to the input signals and they are not phase aligned to each other, so the buffer output is not clean.

That impacted the PLL output as well.


Regards.


  • Joossss's avatar
    Joossss
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hey!

    Thanks this works indeed, I only tried to use this process, because I tried to solve the same issue with it, by introducing delays into one of the lines, because before this I used 

    lvds_clk_p <= not lvds_clk_p after 3.3 ns;
lvds_clk_n <= not lvds_clk_p; -- 150 MHz

    and this also didn't work.

    Anyway, thanks for solving the issue.