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Altera_Forum
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13 years ago

PLL for LVDS with extra output

Hi All,

I have situation where I am trying to produce an extra clock output from a PLL that is producing clocks for LVDS transcievers in a Stratix III. I have an issue with the alignment of the extra clock relative to the reference.

Here is the straightforward part: I have a group of LVDS transceivers where I am using only the transmitters, not the receivers. I generated the LVDS transcievers with "use external PLL" selected. The transmitters are running at 1 Gb/s with 8:1 serialization, so they get a clocks at both 1 GHz and 125 MHz. I have instantiated a PLL that provides the two clocks for the LVDS transmitters plus the third 125 MHz parallel clock used to provide parallel data to the LVDS block. Duty cycle and relative phases are all set up properly and all of this works fine. The reference for this PLL comes from an external pin and is at 62.5 MHz, half of the parallel clock rate.

Now the interesting part: I also need to generate a 62.5 MHz clock that has a deterministic phase relative to the reference and is also in phase with the parallel clock so I can clock data across those domains. To do so, I have used another output from the same PLL and set it up for 62.5 MHz with the appropriate phase. No problem so far.

Because the PLL is used for LVDS, Quartus automatically selects the PLL compensate clock to be the LVDS clock. If I assume nothing about the Altera PLL, this would mean that the LVDS clock will be aligned with the reference and the parallel clock could be aligned any 1 of 8 ways relative to the reference, and the extra 62.5 MHz clock could be in 1 of 16 aligments. However, I have read in the documentation that the parallel clock will always be in the same position relative to the reference. The question is, what about the extra 62.5 MHz clock? Will it also have a deterministic phase relationship to the reference clock? It would seem this would only be the case if the PLL design was very careful about how the output counters come out of reset. I can not find any documentation specifying this behavior.

Any insight would be appreciated.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    The question is, what about the extra 62.5 MHz clock? Will it also have a deterministic phase relationship to the reference clock? It would seem this would only be the case if the PLL design was very careful about how the output counters come out of reset.

    --- Quote End ---

    The same carefulness is required to have the LVDS fast and slow clock synchronized. Achieving fixed phase relation between all outputs is in fact a feature of the Altera PLLs and can be expected to work in your design as well.

    I have sometimes difficulties to understand how the LVDS settings are translated into PLL parameters. In this case it's helpful to review the PLL tab in the compilation report.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thank you, FvM, I appreciate the response.

    To confirm, I wrote some code to do what I described on the Altera Stratix III development board, and every output of the PLL including the extra one always had the same phase alignment through 10 power cycles.

    As to the PLL settings, I have initially found them confusing too. There are a couple of Altera Solution IDs in the knowledge base that were helpful to me. In case anybody else finds them helpful, they are:

    Altera Solution ID rd07142008_32

    Atera Solution ID rd11212007_95