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Honored Contributor
Honored ContributorPLL for LVDS with extra output
Hi All, I have situation where I am trying to produce an extra clock output from a PLL that is producing clocks for LVDS transcievers in a Stratix III. I have an issue with the alignment of t...
Altera_ForumHonored Contributor
Honored ContributorThank you, FvM, I appreciate the response.
To confirm, I wrote some code to do what I described on the Altera Stratix III development board, and every output of the PLL including the extra one always had the same phase alignment through 10 power cycles. As to the PLL settings, I have initially found them confusing too. There are a couple of Altera Solution IDs in the knowledge base that were helpful to me. In case anybody else finds them helpful, they are: Altera Solution ID rd07142008_32 Atera Solution ID rd11212007_95
