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The question is, what about the extra 62.5 MHz clock? Will it also have a deterministic phase relationship to the reference clock? It would seem this would only be the case if the PLL design was very careful about how the output counters come out of reset.
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The same carefulness is required to have the LVDS fast and slow clock synchronized. Achieving fixed phase relation between all outputs is in fact a feature of the Altera PLLs and can be expected to work in your design as well.
I have sometimes difficulties to understand how the LVDS settings are translated into PLL parameters. In this case it's helpful to review the PLL tab in the compilation report.
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