Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

PLL example

Dear all,

I would like to prepare a simple design in order to show to students the importance of PLL.

In order to be useful it is important that the design is not a huge one otherwise the students miss the PLL in the numerous problems the rest of the design poses.

I thought of a 1 bit serial input stored in a shift register at Fck frequency.

The content of the shift register is then transferred in parallel to a register using a clock that is N times slower than Fck (Fck/N = Fslow).

I prepared a design that generates Fslow with a frequency divider (counter).

A second design generates Fslow with the altPLL IP.

In my hope I would find that the second design has much better timing (higher Fmax).

However I found the following issues:

1) The design using a counter is very fast. It is limited by input pin transition time, not by the internal delay.

2) The PLL lock range is limited and hence I'm not able to go to very high freqeuncy.

The net result seems to be that the design using the counter is better than the one using the PLL.

I have two questions:

1) Do you see any error in my analysis of the two designs?

2) Do you have a better example using a PLL that can be used for teaching purposes?

Thx

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    - Hard to tell what's going on without some number and more details of what you're seeing. Note that the TimeQuest won't propogate a clock through a ripple clock divider(which is what I assume you used), so your divided counter might not be constrained at all.

    - For the described design, the major benefit of the PLL is not the individual clocks, but the transfer from the main clock to the divided clock. Your layout will have huge skew, while a PLL would provide two edge-aligned clocks, making for easier transfers.

    - That being said, a PLL isn't necessary. The same thing could be done using a clock enable to make a slower clock.

    - Perhaps making the second clock faster is more straightforward, since that is near impossible to do in logic, where a PLL has no problem. Or make it a strange ratio, like 5/8ths. (Fractional PLLs will be able to do almost any clock...)

    - The two major benefits are creating new clocks and reducing PVT variation of the clock tree, which helps I/O timing. For example, a design with a single clock domain and no PLL might have a Tco of 8ns in the slow corner and 4ns in the fast corner. Using a PLL might make it a Tco 5ns in the slow and 4ns in the fast(I'm making up numbers) so the variation went from 4ns to 1ns. (A PLL makes Tcos faster, but it also makes Tsu values slower by the same amount, but being able to phase-shift let's you get whatever I/O timing you want)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Your criteria of Fmax has nothing to do with counter/PLL performance. Fmax is calculated from 1/min clock period and depends on tSU of internal registers ...etc i.e. irrespective of clock source.

    tH may be better criteria as it depends on clock delay issues.

    Fmax = lowest of 1/[reg tCO + reg tSU + (data delay – clk delay)] across all launch/latch pairs.

    Unless clock jitter is too much (affects tCO and clock delay factors) then it is irrelevant what is sourcing the clock.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The benefits of PLL over counter are:

    - avoid clock gating problems

    - efficient control of phase

    - higher clock rates than source

    - jitter (not sure)