PLL example

- Hard to tell what's going on without some number and more details of what you're seeing. Note that the TimeQuest won't propogate a clock through a ripple clock divider(which is what I assume you used), so your divided counter might not be constrained at all.

- For the described design, the major benefit of the PLL is not the individual clocks, but the transfer from the main clock to the divided clock. Your layout will have huge skew, while a PLL would provide two edge-aligned clocks, making for easier transfers.

- That being said, a PLL isn't necessary. The same thing could be done using a clock enable to make a slower clock.

- Perhaps making the second clock faster is more straightforward, since that is near impossible to do in logic, where a PLL has no problem. Or make it a strange ratio, like 5/8ths. (Fractional PLLs will be able to do almost any clock...)

- The two major benefits are creating new clocks and reducing PVT variation of the clock tree, which helps I/O timing. For example, a design with a single clock domain and no PLL might have a Tco of 8ns in the slow corner and 4ns in the fast corner. Using a PLL might make it a Tco 5ns in the slow and 4ns in the fast(I'm making up numbers) so the variation went from 4ns to 1ns. (A PLL makes Tcos faster, but it also makes Tsu values slower by the same amount, but being able to phase-shift let's you get whatever I/O timing you want)