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Altera_Forum
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14 years ago

PLL example

Dear all, I would like to prepare a simple design in order to show to students the importance of PLL. In order to be useful it is important that the design is not a huge one otherwise the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Your criteria of Fmax has nothing to do with counter/PLL performance. Fmax is calculated from 1/min clock period and depends on tSU of internal registers ...etc i.e. irrespective of clock source.

tH may be better criteria as it depends on clock delay issues.

Fmax = lowest of 1/[reg tCO + reg tSU + (data delay – clk delay)] across all launch/latch pairs.

Unless clock jitter is too much (affects tCO and clock delay factors) then it is irrelevant what is sourcing the clock.