PLL creation with IP Catalog (refclock less than 5MHz)

Hi,
besides frequency range problem, PLL can only synchronize to a continuous clock signal. Red encircled signal rather requires some kind of CDR circuit that reconstructs a continuous clock matching signal edges. Cyclone V has no hardware CDR features, soft CDR can be however implemented utilizing PLL dynamic phase shift.

Regards
Frank

P.S.: Not sure if you need to exactly synchronize to signal clock. If you just want to decode the (apparently Manchester encoded) data stream, an UART approach with sufficient oversampling ratio is probably the straightforward way.