PLL creation with IP Catalog (refclock less than 5MHz)

The FPGA I'm working with will act as a receiver for a wireless 3.75MHz signal. The signal will be transmitted by another FPGA. (attached is a screenshoot of the waveform of the 3.75MHz signal).

Therefore, I need to recover the 3.75MHz clock from the signal wave itself and assure it will be phased by 90 degrees so we can perform the signal deserialization later on.

Even though we'll use the 50MHz standard clock for the board operation, our plans were having both refclock and output clock set as 3.75MHz. Refclock as the signal wave received and output clock as the original clock signal phased by 90 degrees.

As far as I know, that configuration is feasable due to our PPM signal having only two positions (0 or 1), but IP megawizard is preventing me from creating a PLL with a refclock lower than 5MHz and confirm if the component would work as intended.

Is there a way to generate a PLL through IP catalog with refclock lower than 5MHz?