PLL clock output pins vs. regular I/O pins?

The advantage of the PLL output pins is that they have dedicated, characterised routing. This allows you to, very accurately, control the phase of the clocks being driven from these pins. This becomes a major advantage particularly if you're clocking a synchronous interface to another device. This sounds relevant for both your interfaces.

As soon as you drive a PLL clock out of a standard I/O pin you're subject to all the routing delays incurred in getting the clock to the I/O pin. Depending on your clock frequency, you're likely to find it very difficult to constrain your design appropriately.

Have a read of the 'cyclone iv pll hardware overview' section, page 5-20, in the clock networks and plls in cyclone iv devices (http://www.altera.com/literature/hb/cyclone-iv/cyiv-51005.pdf) chapter of the Cyclone IV datasheet.

As for which PLL will be used (from the same datasheet):

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Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.

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and 'PLL1_output' is associated with PLL1 etc.

Cheers,

Alex