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william7's avatar
william7
Icon for New Contributor rankNew Contributor
3 years ago

PLL clock output for SDRAM is not connected

I'm mapping my VHDL design to Cyclone IV device. The SDRAM clock is derived from altpll's 2nd clock output. The compilation generates a warning message: Warning (15899): PLL "clkgen:clkgen0|cyclone...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.