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Altera_Forum
Honored Contributor
Honored ContributorPlease help with PLL
Hello! I'm trying to use PLL to increase frequency of my system. I use Quartus 17 and de0-nano-SoC board. Steps I did: 1. On my IP catalog I chose Altera PLL: https://screencast.com/t/nshqodh...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Yes, it works fine, when I use just clk (it comes from V11, https://screencast.com/t/bdsshstrk ) Is it true that pll_reset is not necessary to start pll? --- Quote End --- You better double check naming and mapping as I see some differences between your naming above and those in your pll link reset is optional so you can keep it released for now but also add pll lock output to see if it works.
