Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Please help me about the Cyclone 3. EP3C10TQ144

EP3C10TQ144

I've never used FPGA.

I have a problem with the use of Cyclone 3.

How to use JTAG.

How DIY JTAG cable that goes from the computer.

Now I have to create your own board.

I do not understand that Q nstatus, CONF_DONE is low at all times.

Program FPGA I have not done it.

But the problem is the AP most of my design wrong I'll try to a JTAG.

And if possible would like to see examples of design

I promise to try to turn to the FPGA.

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I don't understand what you are looking for. How can you know that CONF_DONE is low at all times if you haven't created your board yet?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Sorry I'm not good at English Language.

    board Completed.

    R 4.7k to VCC through CONF_DONE pin.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    nStatus, CONF_DONE (and IO_INIT_DONE) should all be tied to VCC with a resistor (10k here).

    What tells you CONF_DONE is low?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    nStatus, CONF_DONE (and IO_INIT_DONE) should all be tied to VCC with a resistor (10k here).

    What tells you CONF_DONE is low?

    --- Quote End ---

    I use a Multimeter measure (^_^)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I think the layout circuit fault.

    Please suggest ways to design

    In design time I do not have jtag.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You should always have a JTAG connection, it can really help.

    How do you configure the FPGA? Check the signals with a scope. You should also read Altera's recommendations and compare them with your schematic.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I is not done it since the beginning.

    I was assigned to. But when he came up to me to fix the problem.

    I looked at the manual. I saw that what they have done deficiency

    Now I have the problem somewhat.

    But what I want now is that I want to cut the rest. Out to only FPGA.

    Try the program before.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Can't you modify the board and solder a JTAG connector with the required pull ups/downs directly on the FPGA pins? It isn't very nice, but if it is just to test your design...

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    umm nStatus, CONF_DONE is low all time

    IO_INIT_DONE must be R10k to VCC yes or no ?