please explain use of set_output_delay

At first glance I thought the "Fastest" and "Slowest" regions were the data transition region, not the data valid window. Now that you mention it, I see that the diagram makes more sense for them to be the data valid window. Sorry for the confusion. I'll risk confusing people further by describing how the diagram would look for a more general case.

I just now noticed that there are 2 pages in the attachment. I'm looking only at page 1.

I'm guessing that the "Fastest" and "Slowest" labels mean the fast timing model (fast process/voltage/temperature) and the slow timing model (slow PVT).

In reality, there is a data transition region between the data valid windows for two consecutive clock cycles even for a single PVT. If you extend the diagram to show the data for the second clock cycle, you see that the diagram has zero data transition time for each of "Fastest" and "Slowest". That's what Quartus will give you for a single pin for the typical case of a register driving the output pin directly (no logic between the register and pin that can create more than one possible delay from register to pin). In general, however, there is a data transition region even when looking at a single timing model. For a single pin, logic between the register and pin can (but won't necessarily) make the transition region be longer than zero. If the diagram represents an output bus, you will get a nonzero transition region across the bus even if the registers are all in the I/O cell with no logic after them.

You have a maximum tco to the left edge of the data valid window for both the fast and slow timing models. You usually care only about the one for the slow timing model, which is the one labeled in the diagram.

You have a minimum tco to the right edge of the data valid window (the hold time provided for the old data, or where transitions can start for the next data) for both the fast and slow timing models. You usually care only about the one for the fast timing model, which is how the diagram is labeled for a data transition region of zero length. The Min_Tco arrow is really to the right edge of the data valid window for old data and the start of the data transition region for new data. That happens to be the same as the left edge of the data valid window for new data for the common case of zero data transition time for a single pin at a given PVT.

What really matters for most designs is the data valid window and data transition region over PVT. In the diagram, the data valid window over PVT lasts from where the Max_Tco arrow is drawn to where the Min_Tco arrow would be if redrawn for the next clock cycle. The data transition region is from the Min_Tco arrow where it is already drawn to the Max_Tco arrow as de-em said in the previous post.

Hello,

Thank you for your feedback, but I think it is OK. Because the min tco is the earliest time when the data arrives and the previous data becomes invalid. If it is better to make min and max tco together give the transition region, shouldn't min tco point right and max tco point left boundary as attached?

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# # I'm sorry. I didn't read the last post from Brad before I wrote this post. m(_ _)m

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i am just beginner in timing analysis. i would like take ur attachment(rev2) as my reference. Before that, is there any update on it?

May u recommend good article to me?

Hi jasonkee111,

I didn't update the document and it should be still valid.

I have not look into it, but there is a cookbook for timequest. Did you check it?

http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf

Regards

I have look at the http://www.altera.com/literature/man...t_cookbook.pdf (http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf) before. I don really get it due to timing diagram is not available.

I have a few question to ask in ur doc(rev2):

page 1:

1. Why the Min_Tco arrow is put on the latch clock instead of on launch clock?

2. Min_Tco : The earliest time when new data arrives and the data becomes invalid. The data invalid points to old data? If it means to invalid new data, then i have no idea why it is invalid?

3. Why there is different length of arrow for set_output_delay (refer to row 4 and row7)?

4. i am confusing on the arrow direction,new setup time, new hold time and the equation output delay(min and max). From what i understand is to the left means negative and to the right means positive. i don understand other than that.

page2:

1. In the doc rev2 pg2, is FPGA input pin or FPGA output pin? It seems to me is output pin.

The basic is important to me. So, I hope u don mind to explain to me. Thanks a lot.

Thank you gee for your document it's great help!

Hi jasonkee111,

Have you tried to look at this document an433 application note from altera? I think it's better than the cookbook to understand...

To try to answer some of your questions:

1. The min_Tco could be put on the launch clock, or the latch clock for the previous data, it's the same constraint

2. When new data arrives your old data becomes invalid, then yes, the data invalid points to old data

3. The first representation (arrow) only takes in consideration the Tco (max) after the launch edge, the second one adds another constraint which is the hold required time after the latch edge. Another constraint means you have less time, that's why the arrow has different size...

4. No it's not that easy...What gives you the positive or negative sign is the clock edge you're looking at and the type of constraint (does data have to be there before or after the edge...??)

Page 2:

1. we are trying to set output delay here, so clearly it's output pins...

good luck!

Thanks for ur explanation. I did read the AN433.

"(does data have to be there before or after the edge...??)"

What do you mean?

I personally understand it like this:

if we are analyzing the setup constraint in reference to a launch edge, then data has to be there before the setup delay constraint, so the setup constraint value will be added to the data propagation delay and that's the output delay maximum.

now if we are looking at the hold constraint then data will have to remain there after the launch edge, so the hold value will be cut out from the data propagation delay.

Everyone, please correct me if i am mistaking!!