Honored Contributor
Honored ContributorI have look at the http://www.altera.com/literature/man...t_cookbook.pdf (http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf) before. I don really get it due to timing diagram is not available.
I have a few question to ask in ur doc(rev2): page 1: 1. Why the Min_Tco arrow is put on the latch clock instead of on launch clock? 2. Min_Tco : The earliest time when new data arrives and the data becomes invalid. The data invalid points to old data? If it means to invalid new data, then i have no idea why it is invalid? 3. Why there is different length of arrow for set_output_delay (refer to row 4 and row7)? 4. i am confusing on the arrow direction,new setup time, new hold time and the equation output delay(min and max). From what i understand is to the left means negative and to the right means positive. i don understand other than that. page2: 1. In the doc rev2 pg2, is FPGA input pin or FPGA output pin? It seems to me is output pin. The basic is important to me. So, I hope u don mind to explain to me. Thanks a lot.
