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Altera_Forum's avatar
Altera_Forum
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14 years ago

Please explain the following

I have one line in my VHDL test bench file as follows CONV_STD_LOGIC_VECTOR(16#100#+I*2,16) in for Loop integer I. Could anyone please explain how can I plot this in waveform, I know so...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

BUS_ADDR_I already is an address bus.

I still dont understand what you are trying to do.

Are you trying to wait between loop iterations? 


for I in 0 to 15 loop
  BUS_ADDR_I <= CONV_STD_LOGIC_VECTOR(16#100#+I*2, 16);
  wait until rising_edge(clk) ;
end loop;