Forum Discussion
Altera_Forum
Honored Contributor
8 years agoThe first issue is a timing constraint issue. It sounds like you're missing a clock constraint for that clock in your .sdc file.
For your second question, if this extra logic is to be accessible by the Arm processor, you need to connect them to a processor bridge (regular or lightweight) or use the additional GPIOs to the processor available from the FPGA manager of the HPS. If this extra logic does not need to be accessed by the HPS and you're asking about just connecting it to I/O pins, that would be handled in the Pin Planner. Setting up HPS dedicated pins as loaner I/O makes them available to FPGA logic.