Honored ContributorIn the pin planner one has the option to define a node in the “reserved” column.
When a reserved state is selected does that act as if the pin has actual logic tied to it when the fitter is run even if the logic is not yet defined? I need to finalize my schematic and I would like to make sure there are no conflicts in the pin assignments I have chosen but I really won’t complete the VHDL yet
Honored ContributorA reserved pin does not add any logic to your design. It is only to be connected for future assignment and as such helps the tool analyze your design io better from the start. The tool will know about that pin (in/out/bidiectional/unused) so you don't get surprise difference once you use that reserved pin.
Honored Contributori use a combination of IP instantiations and Virtual Pins/Empty partitions when doing an FPGA pin out. the IP helps with complex I/O and clocking requirements (memory, transceivers). for GPIO inputs i use a real input pin connected to a Virtual Pin output, and for GPIO outputs i use a real output pin driven by a Virtual Pin input. this helps avoid potential problems like trying to drive a pin that doesn't have an output buffer (clock input)
unfortunately i think Virtual Pins and Empty partitions are both part of Incremental Compile which is part of Subscription Edition
