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Altera_Forum
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14 years ago

Pin planner "reserved" column

In the pin planner one has the option to define a node in the “reserved” column. When a reserved state is selected does that act as if the pin has actual logic tied to it when the fitter is run ev...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

i use a combination of IP instantiations and Virtual Pins/Empty partitions when doing an FPGA pin out. the IP helps with complex I/O and clocking requirements (memory, transceivers). for GPIO inputs i use a real input pin connected to a Virtual Pin output, and for GPIO outputs i use a real output pin driven by a Virtual Pin input. this helps avoid potential problems like trying to drive a pin that doesn't have an output buffer (clock input)

unfortunately i think Virtual Pins and Empty partitions are both part of Incremental Compile which is part of Subscription Edition