Pin placement with altera lvds core

Honored Contributor

9 years ago

You won't find "translate pins to lvds locations" in the datasheet.

PLLs are instantiated by default for ALTLVDS blocks.

Please open the following document

Go to clock networks and plls in cyclone v devices

Go to for ex, pll locations for cyclone v e a2 and a4 devices

You should find the following pic

Study this pic, but of course search in the document for your chip.

These pictures helped me a lot design a good board.

As I said, ALTLVDS uses PLL. So you think of using the PLLs. You can write a custom code without ALTLVDS but use PLLs to test the operation.

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