Pin location is too close to PLL clock input pin

This error could be due to the EMI considerations/interference of Clock pins. In general, we do not route any other signal pin or even another clock pin close to a high frequency clock as it may cause the signal in question to shift/toggle in an unwanted manner causing glitches to appear in the output. In ASIC we normally add in a layer of isolation between clock pins/routes and other signal routes to prevent this interference.

In FPGAs we can avoid this situation by separating the pin assignments for clock inputs/outputs from the PLL and other signals. I guess, it's not always possible to do so after the board has been designed, but in general these considerations will be done during Board design in order to place a "safe" distance between the free running HF clocks and other sensitive signals.

If you get this error from the tool, check if you can ignore this and proceed with the bit file generation, if not, you will have to change the signal pin placement and move it away from the PLL clock inputs/outputs.

-Abr