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Honored Contributor
Honored ContributorPin location is too close to PLL clock input pin
Hello everybody, i'm using an FPGA 10M25SCE144I7G and i found this problem: the output xxx in pin location 27 is too close to PLL clock input pin in pin location 26. Is it possible to disre...
Altera_ForumHonored Contributor
Honored ContributorHello,
I have similar issue.. Error (18496): The Output o_ctrl[0] in pin location 92 (pad_5895) is too close to PLL clock input pin (i_reset_l) in pin location 91 (pad_0) In Assignment editor, I've set I/O Maximum Toggle Rate to 0 mhz for both o_ctrl[0] and i_reset_l, but am still getting error. Is there a way to tell Quartus not to analyze signal integrity for these two signals?
