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Honored Contributor
Honored ContributorPin location is too close to PLL clock input pin
Hello everybody, i'm using an FPGA 10M25SCE144I7G and i found this problem: the output xxx in pin location 27 is too close to PLL clock input pin in pin location 26. Is it possible to disre...
Altera_ForumHonored Contributor
Honored ContributorIf it is a fixed logic level then I think you'll be fine.
