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Altera_Forum's avatar
Altera_Forum
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15 years ago

Pin Damaged question

hello,

we are using altera Cyclone1 EP1C6..

we use the IC in an I/O application..

the I/O pins of the IC are connected to external device and user can touch these pins by touching the end of the cable..

we noted after sometime that a pin damaged and became shorted to the ground inside the Cyclone itself..we are sure that the short is inside the IC not out on the board..

how can that happen??

and how to protect the I/O pins of the FPGA to not damage any more??

and how the short is still exist even we disconnect the power from the FPGA,is it volatile??

please we need help!

thank you..

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    how can that happen??

    --- Quote End ---

    It can be easily achieved by applying a sufficient high overvoltage or overcurrent to the respective pin.

    --- Quote Start ---

    and how the short is still exist even we disconnect the power from the FPGA,is it volatile??

    --- Quote End ---

    Simply assume, that a semiconductor structure inside the chip, e.g. an output transistor has been destroyed by applying too much energy and forms a permanent short now.

    --- Quote Start ---

    and how to protect the I/O pins of the FPGA to not damage any more??

    --- Quote End ---

    Design a circuit, that keeps the FPGA's specified maximum ratings in any situation. Exposing FPGA pins directly to "outer world" should be avoided if possible, but with well designed protection networks, it can be safe.
  • Altera_Forum's avatar
    Altera_Forum
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    thank you for your reply..

    our application requires that the IO pins are out to the outside world..

    so, can you help me suggesting some protection circuits?
  • Altera_Forum's avatar
    Altera_Forum
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    ESD protection devices dedicated to fast I/O, e.g. NXP IP4220CZ6 can provide some additional protection, or schottky clamp diodes. The best solution depends a lot on the respective I/O signal characteristic.

  • Altera_Forum's avatar
    Altera_Forum
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    thanks alot..

    I read the datasheet of the IC of NXP but there is a question about the PIN number 5 VP (supply voltage), I do not understand can it be 3.3V??

    I can not send the link because my post count must be 5 or greater

    but it is at

    nxp.com/documents/data_sheet/IP4220CZ6.pdf
  • Altera_Forum's avatar
    Altera_Forum
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    I know the datasheet. You can use it with lower VCC, but the Z-diode won't limit the supply voltage above 3.3V. The clamp diodes are working anyway. You may be able to find dedicated 3.3V protection components.

    You didn't yet tell about the involved interface standard and why you don't see an option to place any kind of buffer between the FPGA and the external connector.
  • Altera_Forum's avatar
    Altera_Forum
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    thank you for your answers..

    the I/O standard is 3.3LVTTL or 3.3LVCMOS.

    and the application is writing and reading data to and from this connectors..

    the IO pins are already connected to Pullup resistances outside the FPGA and the IO pins are open drain.. and the supply voltage is 3.3V.

    but I do not understand something..

    the function of the zener diode is to limit the voltage to 3.3V(VP), is n't it?

    so any voltage above this value will be clipped to this value(3.3)..

    is that true?

    and the diodes are to eliminate the effect of the ESD(electrostatic discharge)..

    will it work with this value(3.3V) ?
  • Altera_Forum's avatar
    Altera_Forum
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    I get this IC from NXP PESDXS4UD its description is

    (

    Quadruple ElectroStatic Discharge (ESD) protection diode arrays in a SOT457 (SC-74)

    small Surface-Mounted Device (SMD) plastic package designed to protect up to 4 signal

    lines from the damage caused by ESD and other transients.

    )

    will it work without the zener diode?