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VYoung's avatar
VYoung
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3 years ago

Phased Clock

Are there any Intel SoC FPGAs that provide a clock manager with different phased clock outputs? e.g. One 100 MHz input with four 200 MHz phased outputs (0 degree, 90 degrees, 180 degrees, and 270 deg...
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VYoung's avatar
VYoung
Icon for New Contributor rankNew Contributor
3 years ago

Hi Teh,

I found the following PLL Block Diagram for the Intel FPGAs:

It kind of implies that there are only 2 clock outputs for the PLL. My design uses 4 phase shifted 200 MHz clock outputs (0, 90, 180, 270 degrees phase shift). The input clock is 100 MHz. Can the PLL hard core provide this? You mention the PLL Soft Core IP can provide this, but will the PLL Soft Core IP use a lot of fabric resources?

Thanks,

VYoung