Phase Relationship after PLL reconfiguration in CycloneIV

Thanks for your reply.

the doc you point to is about 28-nm devices, not CycloneIV, i think cycloneIV is very different to CycloneV device.

and you mean when resetting PLL(hold areset high for some time), the phase relationship will revert back to the setting which i initially set in megawizard?

according to the signals grasped by oscilloscope, this is not the case.

i set the original phase relationship to 0 degree, however, when i reconfigure PLL to a different frequency(in this process, i hold areset high, then released), then check the phase relationship, i found there is a phase shift between two clocks, and this puzzles me much. further more, when i reconfigure to another frequency, the phase shift also changes!

another point i want to clear is that i directly register in the 144-bit chain to reconfigure the PLL to change the output frequency, the output frequency is correct everytime which i checked with oscilloscope.

is there any document discuss this issue?

or did i miss something?

thanks,

ingdxdy