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Honored Contributor
Honored Contributorphase delay of PLL
hello, i am implementing a PLL in EP3C16. there is round 2.5ns delay between the input reference clock and output clock. it seems that cyclone series FPGA including I,II,III all have a phase del...
Altera_ForumHonored Contributor
Honored ContributorIf you connect your output to a dedicated PLL output pin ( the ones with an (L) in the pin-planner) you can set your PLL to compensate for this pin aligning the output clock with the input clock. See "Zero Delay Buffer Mode" on page 78 in the Cyclone III Device Handbook.
