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Honored Contributor
Honored Contributorphase delay of PLL
hello, i am implementing a PLL in EP3C16. there is round 2.5ns delay between the input reference clock and output clock. it seems that cyclone series FPGA including I,II,III all have a phase del...
Altera_ForumHonored Contributor
Honored ContributorIn general FPGA PLLs offer phase shift feature meausured in degrees or time with various degrees of step resolution.
zero phase is just one value of phase that = 0 zero phase buffer is the term used for having same clk output at same freq and phase as input and does not need external loop (fbin is only needed if you don't like the internal fpga analogue loop). If you mean to offset 2.5 ns between input clk and output then apply negative delay of -2.5ns
