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Matt1's avatar
Matt1
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7 years ago

PFL Mega Function: Setup time Issue

hi all, I am trying to implement Altera PFL IP (configuration is done for FPPx16) in MAX5 CPLD. As per the datasheet i did all the constraining for the respective signals. From the CPLD design com...
GuaBin_N_Intel's avatar
GuaBin_N_Intel
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7 years ago

This is resource limitation in your device part number. If you can't choose a larger max device, ​I think the option you have is to reduce the running core speed.

Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

hi GNg,

I solved the timing issues which were reported by the Quartus by changing the seed value and Fitter settings in the tool.

now the tool reports Fmax as 100.2Mhz

Thanks for your support