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Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

PFL Mega Function: Setup time Issue

hi all, I am trying to implement Altera PFL IP (configuration is done for FPPx16) in MAX5 CPLD. As per the datasheet i did all the constraining for the respective signals. From the CPLD design com...
GuaBin_N_Intel's avatar
GuaBin_N_Intel
Icon for Contributor rankContributor
7 years ago

Have you tried to set IP GUI>Flash Programming>Speed? Also, set the fitter>optimization mode(performance) but it may have little help.

No, there is no UG stated Fmax of PFL IP in any device. It is soft IP and we have varies product range and families. What you can do is to run a compile with standalone PFL and see the Fmax you get.