Forum Discussion
Matt1
Occasional Contributor
Occasional ContributorPFL Mega Function: Setup time Issue
hi all, I am trying to implement Altera PFL IP (configuration is done for FPPx16) in MAX5 CPLD. As per the datasheet i did all the constraining for the respective signals. From the CPLD design com...
GuaBin_N_Intel
Contributor
ContributorYes, Alex is right. Refer to UG here https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf, 1.4.2.4, Table7, Fmax of IP core clock depends on which device and speed grade you are targeting. You can check the Fmax in slow corner from TQ report. There is no other optimization setting can be done for the internal path.
