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Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

PFL Mega Function: Setup time Issue

hi all, I am trying to implement Altera PFL IP (configuration is done for FPPx16) in MAX5 CPLD. As per the datasheet i did all the constraining for the respective signals. From the CPLD design com...
a_x_h_75's avatar
a_x_h_75
Icon for Contributor rankContributor
7 years ago

From the user guide for the PFL:

"Any reference to the core clock speed of 100 MHz is only an example of the configuration time calculation and not a recommendation of the actual clock."

The PFL IP isn't necessarily designed to run at 100MHz. This depends entirely on the device in which you're trying to run it. It will run at 100MHz in the right device. However, it may well not run at 100MHz in the device you've chosen.

Cheers,

Alex